This application claims priority from Korean Priority Document No. 2001-30750, filed on Jun. 1, 2001, which is hereby incorporated by reference in its entirety.
1. Field of the Invention
This disclosure relates to an electrically programmable and erasable nonvolatile semiconductor memory device and, more particularly, to a nonvolatile semiconductor memory device having selective multiple-speed operation modes.
2. Description of the Related Art
Semiconductor memory devices are generally classified into two groups, that is, volatile semiconductor memory devices and non-volatile semiconductor memory devices. The volatile semiconductor memory devices are further classified into a dynamic random access memory and a static random access memory. The volatile semiconductor memory devices have rapid read and write speeds. However, if the volatile semiconductor memory devices are not continuously supplied with external electric power, data stored in the memory cells are eliminated.
Non-volatile semiconductor memory devices are classified into a mask read only memory (MROM), a programmable read only memory (PROM), an erasable and programmable read only memory (EPROM), and an electrically erasable programmable read only memory (EEPROM).
Even though the non-volatile semiconductor memory devices are not supplied with an external electric power, the devices permanently maintain data stored in memory cells and are accordingly used in storing data to be stored regardless of supply of an electric power. However, a user cannot freely write (or program) and read with an electronic system itself provided therein with the MROM, PROM, and EPROM. That is, it is not easy for a user to erase or reprogram the already programmed data once it is mounted on a board.
However, since the EEPROM can be used in a system in which erasing and writing are electrically performed, it is on an increasing trend that the EEPROM is applied to a supplementary memory device or a system-program storage device that continuously requires renewal of data. That is, various electronic devices that are controlled by recent computers or microprocessors more and more require development in EEPROMs that can be erased and programmed often. Furthermore, since using a hard disk device having a rotational magnetic disk as a supplementary memory device occupies a comparatively large space in a potable computer or battery powered computer such as a notebook computer, computer designers are turning their interest to developing EEPROMs that occupy a small space. That is, designers are interested in a high concentrated and high performance EEPROM.
In order to achieve a highly concentrated EEPROM, there is a problem that the space occupied by memory cells in the EEPROM should be reduced. To solve the problem, EEPROM memory cells having a NAND structure were developed by which the number of contact holes between bit-lines and the number of selection transistors per cell can be reduced. Such a NAND structure cell is disclosed for instance, on pages 412 to 415 of IEDM published in 1988, under the title of xe2x80x9cNEW DEVICE TECHNOLOGIES FOR 5Vxe2x80x94ONLY 4 Mb EEPROM WITH NAND STRUCTURE CELLxe2x80x9d, the contents of which are herein incorporated in their entirety.
As EEPROM design techniques have continuously been improved, a NAND type flash EEPROM having a flash erase function has appeared. Since the NAND type flash EEPROM can be easily integrated and made at a low cost relative to the NOR type or AND types of EEPROMs, it is advantageous to apply the NAND type flash EEPROM it to a large scaled supplementary memory device. Recent markets require various NAND-type flash memories and accordingly, various functional options need to be provided at the design time of the NAND type flash memory to comply with the various requirements.
The cell array structure of the NAND type flash memory having characteristics described above will be explained below.
FIG. 10 illustrates the cell array structure of the typical NAND type flash EEPROM and the NAND type flash cell strings.
As shown in the left side of the drawing, the NAND flash memory device includes a memory cell array 950, a row decoder 960 for receiving input addresses and selecting a word line W/L, a page buffer 970 connected to each of bit lines B/L to input/output data to the selected memory cell, and a column decoder 980 for column decoding.
The memory cell array 950 includes a plurality of cell array blocks 951, 952, 953 having a plurality of cell strings. That is, the memory cell array 950 is formed of a plurality of block units, and one block comprises a plurality of memory cell transistors formed of cell strings, for instance, memory cell transistors of 4 Kbyte unit. Referring to the right side of the drawing, it shows a plurality of cell strings in the cell array block.
The basic unit of the NAND type flash memory cell array is cell string (sometimes called a xe2x80x9cNAND cell unitxe2x80x9d). One cell array block includes a first select transistor 900 connected to a corresponding bit line at its drain through a contact hole, a second select transistor 901 connected to a common source line GSL at its source, and a plurality of cell strings formed with n memory transistors M1, M2, . . . , Mn that have drain-source channels series connected between the source of the first select transistor and the drain of the second select transistor. The first select transistor 900 serves to connect or disconnect a selected cell string with bit line B/L, and the second select transistor 901 is used as a ground path of cell string. The NAND type cell string is typically formed on a P type semiconductor substrate, and each of the memory cell transistors has a floating gate formed on a gate oxide film at a channel region between its source and drain regions and a control gate formed on the floating gate. A plurality of word lines W/L are arranged at a first direction, a horizontal direction for instance, to select memory cell transistors M1, M2, . . . , Mn having floating gates in the cell strings and a plurality of bit lines B/L are arranged at a direction perpendicular to the first direction, a vertical direction for instance. The WLs are electrically connected to control gates of the memory cell transistors, and practically play the role of the control gate.
In order to program the memory transistor selected in the cell string, all memories of transistors in the cell string are erased at once, and a programming operation is performed. Such a simultaneous erasing operation of all the memories (commonly known as a flash erase) can be performed by supplying 0 Volts to all the control gates and 20 Volts to the P type well region and the N type substrate, so that the selected memory transistor is programmed by Fowler-Nordheim tunneling (F-N tunneling) through holes from the drain to the floating gate. Thereby electrons are uniformly discharged from the floating gates of the memory transistors to the P type well. As a result, the threshold voltage of each of the memory transistors becomes a negative voltage of approximately xe2x88x924V and the transistor is in a state of depletion by which a binary logic xe2x80x9c1xe2x80x9d is considered stored.
In order to program the selected memory transistor in the NAND cell unit, 20V is applied to a gate of the first select transistor and a control gate of the selected memory transistor, 0V is applied to a gate of the second select transistor, and a middle voltage of 7V is applied to a control gate of each of the non-selected memory transistors.
If the selected memory transistor is written or programmed by a binary logic xe2x80x9c0xe2x80x9d, 0V is applied to bit-lines connected to the NAND cell unit and electrons are accordingly implanted onto a floating gate of the selected memory transistor, thereby the transistor is changed into an enhancement mode. In contrast, if the selected memory transistor is programmed by a binary logic xe2x80x9c1xe2x80x9d, a middle voltage of 7V that corresponds to a program preventing voltage is applied to the corresponding bit-lines, thereby preventing the program operation in the selected memory transistor.
In such a manner, the selected memory transistors are programmed by F-N tunneling of holes from the drain of the transistor to floating gate.
In the memory cell array structure of the NAND flash memory as described above, the memory cell transistors connected to a common word line at their control gates are called pages, and a plurality of pages that are connected to a same string line SSL are called a block.
Generally, data read and program operations are performed by a page unit and erase operation is performed by a block unit.
The size of the page and the size of the block are predetermined when the hardware of the flash memory is designed. Unlike the NOR type flash memory that can be read by random access of byte (x8) unit or word (x16) unit, the NAND type flash memory detects data by a page unit during a relatively long time (xcx9c10 us) to thereby store the data in the page buffer. The controller connected to the flash memory, CPU for instance, toggles a read enable pin (nREx pin) of the flash memory to thereby patch data stored in the page buffer. In such a way, the flash memory requires a relatively long latency for a read operation, however thereafter, quickly inputs/outputs data stored in the page buffer, thereby having a relatively excellent overall data in/out rate. In the case of the flash memory, the larger the size of the page, the more the data in/out rate increases. However, the size of the page cannot be enlarged to an infinite magnitude in order to increase the data in/out rate. The reason is that if the page size is enlarged, the block size that is a basic unit during erasing operation is also enlarged thereby causing any inconvenience in rewriting a relatively small unit of data.
Accordingly, if a user wishes to rewrite a relatively large scaled data and requires a high data output rate, he should use a flash memory having a large page and large block. If a user wishes to rewrite a relatively small-scaled data, he should use a flash memory having a small sized block. In the case of the flash memory that the page size and the block size are physically determined when its design completes, there is a problem that it takes a lot of time and costs a great deal to design and manufacture separate products in compliance with a user""s requirements to various sizes.
Therefore, an improved technique that satisfies various sizes in the devices without designing and manufacturing separate products whenever a user requires products of various sizes is desired.
Embodiments of the present invention provide a NAND type flash memory device that can properly operate in response to a user""s requirements to page sizes and block sizes, and have various multiple speeds of operation mode according to options.
Some embodiments of the present invention provide the structure and operation method of a NAND type flash memory device having two or more page sizes and block sizes.
Some devices according to embodiments of the invention include:
a memory cell array formed of a plurality of cell array blocks each having a plurality of cell strings;
a multiple-speed mode option part for generating a multiple-speed option signal, and
an addressing circuit for selecting different page sizes and block sizes of the memory cell array in response to a state of the multiple-speed option signal.